Some processing systems employ a multi-link input/output (I/O) interface to transfer data between system modules. For example, a processing system can include a memory subsystem that uses a multilink I/O interface to transfer data from a memory module to a memory controller. Typically, the multi-link I/O interface transfers the data between a source module and a destination module without an accompanying clock signal. The multi-link I/O interface therefore employs clock and data recovery (CDR) techniques to generate a clock signal for capturing the provided data. However, noise on the links (channels) of the interface can change the phase of the received data, potentially resulting in errors in the captured data.
Such errors can be reduced by periodically training the multi-link I/O interface, whereby defined training signals are transmitted along the links (also referred to as channels) and the multi-link I/O interface adjusts the phase of the capture clock signal until a defined pattern is accurately captured. However, the training requires additional hardware, increasing the size of the multi-link I/O interface, and interrupts processing of data transfer transactions, reducing system throughput. In addition, the defined training signals typically are based on predicted noise patterns that may differ from the noise experienced by the multi-link I/O interface, reducing the effectiveness of the training process. Instead of using training signals, the multi-link I/O interface can adjust the phase of the capture clock signal based on transitions (edges) in the data being transferred. However, the data may not include enough transitions in order to accurately phase align the capture clock signal with transitions in the data, resulting in data capture errors.
The use of the same reference symbols in different drawings indicates similar or identical items.